REXRTOH SYHNC100-NIB-22aW-24-P-D-E24-A012

The front-end receives three analogue high-frequency or intermediate frequency inputs via the SSMC connector on the front panel. These inputs are coupled into three Texas Instruments AdS5485200 MHz, 16-bit Analogue-to-Digital (A/D) converters. The resulting digital outputs are then directed to the KINTX hyperscale Field Programmable Gate Array (FPGA) for signal processing, data capture and routing to other modular resources. The TIDAC5688DUC (digital upconverter) and the Digital-to-Analogue (D/A) converter accept either a real or a complex baseband data stream from the FPGA. These are utilized to provide inputs for upconversion, interpolation, and dual D/A layers.

The REXRTOH SYHNC100-NIB-22aW-24-P-D-E24-A012 is a device that consists of three channels with a 200 MHz bandwidth and 16-bit Analogue to Digital Converter (A/D), which includes a multi-band digital down converter (DDCS) and digital up converter (DUC) to two D/A modules that operate at 800 MHz with 16-bit resolution, on XMC modules built on the XilinxKINTX Ultra Scale Fuel Component Board Assembly. This equipment has a wide range of potential uses. The REXRTOH SYHNC100-NIB-22aW-24-P-D-E24-A012 is intended for engineers working with Digital Radio Frequency Memory (DRFM) applications. It digitises the incoming RF input signal through a multi-channel input that possesses the capability of working on signals with a bandwidth of up to 80 MHz. Subsequently, it produces an analogue output version of the RF signal with remarkably low deterministic latency.

The REXRTOH SYHNC100-NIB-22aW-24-P-D-E24-A012 boasts three A/D acquisition IP modules to ensure simple data capture and transfer. Each IP module is capable of receiving data from any of the three A/DS or test signal generators. A strong linked-list DMA engine transfers A/D data via the PCE interface using a distinctive capture gate drive mode. In this mode, knowledge of the transfer length specified by the link definition is unnecessary before data acquisition since the acquisition gate length controls it. This mode is particularly advantageous for applications where external gates are responsible for acquisition and the gate’s precise length is uncertain or liable to change. In each A/D acquisition IP module, there exists a robust DDCIP core. The flexible input routing of the A/D acquisition IP modules allows for numerous configurations, such as the possibility of having one A/D driving two DDCs or two A/DS driving their respective DDCs.

For DRFM radar applications, the received radar pulses undergo digitisation and are then transmitted to an FPGA. The FPGA is capable of implementing a range of DSP algorithms, which are used to alter the signal before sending it back to the radar, thereby simulating the reflected pulses. The DSP algorithms are devised to frustrate, mislead or incapacitate the radar, depending on the objectives of the mission. The transmitting radar cannot distinguish this signal from other legitimate signals received and processed as targets, as it consistently represents the original signal. If the signal is stored in memory, it can be used in reactive jamming to create false range targets behind and in predictive jamming to create false range targets in front of the target. Minor alterations are implemented in the frequency-based Doppler shift to fabricate fictitious target velocities. Distortion and manipulation of phase fronts, achieved through the deployment of DRFM, are fundamental in countering angular measurement techniques used in single-pulse radar.