GE IC695CPU315

Description

GE IC695CPU315

GE IC695CPU315

To improve the performance of frame synchronization systems, it is necessary to carefully select frame synchronization code groups and frame structures, and take appropriate protective measures. This article will focus on discussing the use of coherent insertion method to achieve parameter configurable and flexible frame synchronizers, and ultimately implement them using DSP and FPGA hardware. The frame synchronizer is suitable for synchronization code group lengths ranging from 8 to 32 bits, taking into account the performance of the synchronization system; Adapt to single frame and multi frame structures, with variable frame length; The fault tolerance threshold can be adaptively adjusted; Implement fault-tolerant processing of frame filling during pseudo loss of step; It can achieve full frame positive/negative phase changes for BPSK demodulation. The block diagram of the frame synchronizer is shown in Figure 1:
The specific implementation method based on DSP and FPGA frame synchronizer is as follows: 2.1 FPGA implementation function uses FPGA to extract single/sub frame head matching signals, and controls the data flow based on the DSP control signal and outputs corresponding synchronization signals. Due to the high processing speed and built-in ROM advantages of FPGA, it can be used to achieve serial/parallel, parallel/serial conversion of data streams, matching and recognition of synchronization code groups, frame filling, inversion, and other data flow control. It provides single frame and complex frame synchronization signals and word synchronization signals of data, and provides frame matching status signals required by DSP algorithms. The matching recognition of frame headers adopts a large shift buffer, and the DSP controls its matching bits and matching synchronization code groups. The threshold is adjusted based on the system’s capture and tracking status, and matching correlation and threshold judgment are carried out to adapt to different synchronization code groups and fault tolerance requirements. The generation of synchronous signals can be obtained by frequency division, but their universality is not strong and they are not flexible enough. This article uses the internal ROM lookup table in FPGA to generate, which can be flexibly changed according to different frame lengths and structures,

MOTOROLA MVME-162-532
MOTOROLA MVME-162-532A
MOTOROLA MVME-162-533
MOTOROLA MVME-162-533A
MOTOROLA MVME-162P-242/4B
MOTOROLA MVME162-P242L
MOTOROLA MVME162P-242LE
MOTOROLA MVME-162P244LE
MOTOROLA MVME-162P-344E
MOTOROLA MVME-162PA-252SE
MOTOROLA MVME-162-PA-344SE
MOTOROLA MVME167-32A
MOTOROLA MVME-167-33A