GE DS215SLCCG1AZZ01A

GE DS215SLCCG1AZZ01A

GE DS215SLCCG1AZZ01A

At this point, the advantage of DSP for high-performance GPP is that even if a DSP is using cache, which instructions will be put in is determined by the programmer (not the processor), making it easy to determine whether the instructions are read from cache or memory. DSP generally does not use dynamic characteristics such as transfer prediction and inference execution. Therefore, predicting the required execution time from a given piece of code is completely straightforward. This allows programmers to determine the performance limitations of the chip. The 7 fixed-point DSP instruction set is designed with two objectives: to enable the processor to complete multiple operations within each instruction cycle, thereby improving the computational efficiency of each instruction cycle. Minimize the memory space for storing DSP programs (especially important in cost sensitive DSP applications due to the significant impact of memory on the overall system cost). To achieve these goals, the instruction set of DSP processors typically allows programmers to explain several parallel operations within one instruction. For example, in an instruction that includes MAC operations, i.e. simultaneous movement of one or two data. In a typical example, an instruction contains all the operations required to calculate a section of the FIR filter. The cost of this high efficiency is that its instruction set is neither intuitive nor easy to use (compared to GPP’s instruction set). GPP programs usually do not care about whether the processor’s instruction set is easy to use, as they typically use high-level languages such as C or C++. Unfortunately for DSP programmers, the main DSP applications are written in assembly language (at least partially optimized by assembly language). There are two reasons here: firstly, most widely used high-level languages, such as C, are not suitable for describing typical DSP algorithms.

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