GE DS215SDCCG1AZZ01A

GE DS215SDCCG1AZZ01A

GE DS215SDCCG1AZZ01A

Consider an example of digital signal processing, such as a finite impulse response filter (FIR). In mathematical terms, FIR filters are a series of dot products. Take an input quantity and an ordinal vector, multiply between the sliding window of the coefficient and the input sample, and then add up all the products to form an output sample. Similar operations occur repeatedly in digital signal processing, requiring specialized support for devices designed for this purpose, leading to a diversion between DSP devices and general-purpose processors (GPPs): 1. Support for dense multiplication operations GPPs are not designed to perform dense multiplication tasks, and even some modern GPPs require multiple instruction cycles to perform one multiplication. And DSP processors use specialized hardware to implement single cycle multiplication. The DSP processor also adds an accumulator register to handle the sum of multiple products. Accumulator registers are usually wider than other registers, adding additional bits called result bits to avoid overflow. Meanwhile, in order to fully demonstrate the benefits of specialized multiplication accumulation hardware, almost all DSP instruction sets contain explicit MAC instructions. Traditionally, GPP uses a von Neumann memory structure. In this structure, only one memory space is connected to the processor core through a set of buses (one address bus and one data bus). Usually, performing a multiplication will result in 4 memory accesses, consuming at least four instruction cycles. Most DSPs adopt the Harvard structure, which divides the memory space into two parts, storing programs and data separately. They have two sets of buses connected to the processor core, allowing simultaneous access to them. This arrangement doubles the bandwidth of the processor memory and, more importantly, provides both data and instructions to the processor core

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