FTA-554 17-550554-001 Memory Expansion

The FTA-554 17-550554-001 generates chip select or high address signals and uses these signals to page the memory, but will cause inconvenience to the programming when jumping between pages. For CPUs that do not have internal memory and use unified addressing, such as the 80C196KC20 [1], such page switching will cause the CPU to be unable to continue executing the current program and generate an error (see Figure 1). After the CPU performs the page switch operation, it should continue to execute the instruction on page 1, but it incorrectly executes the corresponding instruction on page 2, which is not the desired result. Therefore, finding an effective memory expansion method is an urgent problem in practical applications.

In the use of FTA-554 17-550554-001 series microcontrollers, it was found that 64K bytes of storage space for storing programmes can meet most of the needs (usually less than 10K bytes of the user’s application programme), but if it is used for data storage and control, it will bring about a serious shortage of storage space. Statistical analyses of actual applications have shown that in many cases, access to data is limited to sequential operations.

FTA-554 17-550554-001 takes advantage of this feature to simplify the design of the data storage space, specifically to save address space by performing bulk data access by sequential reads or sequential writes to the same address. In 16-bit CPUs, any section of 64K words (2 to the 16th power) of storage space can be mapped to two addresses (one as the location of the read, one as the location of the write), using this mapping method can be extended to a maximum of 2G words of memory (2 to the 31st power), but such a design at the same time also brings a lot of difficulties in logic control. With the rapid development of programmable logic devices (PLDs) including FPGAs, EPLDE4, CPLDs, etc., the design of digital logic circuits has been greatly simplified so that this memory expansion idea can be realised.