ABB 5SHY5055L0002 3BHE019719R01 IGCT processor module

ABB 5SHY5055L0002 3BHE019719R01 IGCT processor module

ABB 5SHY5055L0002 3BHE019719R01 IGCT processor module

Front-side bus (FSB) frequency (bus frequency) directly affects the speed of direct data exchange between CPU and memory.
There is a formula to calculate, which is data bandwidth=(bus frequency × Data bandwidth)/8, the maximum bandwidth for data transmission depends on the width and transmission frequency of all simultaneously transmitted data. For example, the current Xeon Nocona supports 64 bits, and the Front-side bus is 800MHz. According to the formula, its maximum bandwidth for data transmission is 6.4 GB/s. Difference between external frequency and Front-side bus (FSB) frequency: Front-side bus speed refers to the speed of data transmission, and external frequency refers to the speed of synchronous operation between CPU and mainboard. That is to say, a 100MHz external frequency specifically refers to a digital pulse signal that oscillates 10 million times per second; The 100MHz Front-side bus refers to the data transmission volume that the CPU can accept per second is 100MHz × 64bit ÷ 8Byte/bit=800MB/s. In fact, the appearance of the “HyperTransport” architecture has changed the frequency of the Front-side bus (FSB) in practical sense. Previously, we knew that IA-32 architecture must have three important components: Memory controller hub (MCH), I/O controller hub and PCI hub. Like Intel’s typical chipsets, Intel 7501 and Intel7505 chipsets, are tailored for dual Xeon processors. The MCH they contain provides the CPU with a 533MHz Front-side bus.

With DDR memory, the Front-side bus bandwidth can reach 4.3GB/s. But with the continuous improvement of processor performance, it has brought many problems to the system architecture. The “HyperTransport” architecture not only solves the problem, but also effectively improves the bus bandwidth. For example, the AMD Opteron processor and the flexible HyperTransport I/O bus architecture enable it to integrate the Memory controller, so that the processor can directly exchange data with the memory without passing the system bus to the chipset. In this case, the Front-side bus (FSB) frequency in the AMD Opteron processor does not know where to start.