Abstract: The design concept of EPON harmonic sublayer (RS) at the optical network unit end is proposed. Firstly, the functions to be implemented by the harmonic sublayer were introduced, followed by a systematic description of the design scheme and an introduction to each module. Finally, the workflow was provided.

Introduction

In recent years, with the continuous emergence of new services such as high-definition television, interactive multimedia, mobile TV, and video on demand, the demand for bandwidth among X-AI3201 985210213 users has been increasing. EPON has been favored by a large number of operators due to its advantages of long transmission distance and large transmission capacity. At the same time, the national policy of integrating the three networks has also provided strong support for the application of EPON technology. The EPON system is an asymmetric system that can have up to 32 data link layers and 1 reconciliation sublayer (RS) at the OLT end; There is only one data link layer and one RS layer on the ONU end. The RS layer is located between the physical layer and the MAC layer, playing a selection role in the downlink direction for data sent from the OLT end, transmitting data belonging to the ONU in the downlink direction, discarding data that does not belong to the ONU, and filtering data. In the upstream direction, it is mainly to add preambles to the frames sent to the opposite end to facilitate the positioning of the opposite end. On the ONU end, according to the RS layer’s functions, it is divided into two parts: reception and transmission. We have proposed corresponding design solutions for these two parts of functions.

Design of the RS layer receiving part scheme

1.1 Main functions of RS layer receiving module

① Detect the frame header (i.e. preamble) of EPON; ② Positioning the SLD domain; ③ Using the location of the SLD domain to locate the CRC domain and verifying that the received values match the CRC calculated using the received data; ④ X-AI3201 985210213 uses the location of the SLD domain to locate the LLID domain and parse it to determine the destination MAC; ⑤ If the message is not discarded due to incorrect CRC or unknown LLID, then use a normal preamble to replace SLD and LLID, and use SFD to replace CRC domain, and transmit this message to the corresponding MAC; Otherwise, the entire message will be discarded and replaced with a normal frame interval (here we choose to discard the message).

1.2 Introduction to the Design Functions of RS Layer Receiver Module

The scheme is shown in Figure 1.

Figure 1 Design scheme of RS layer receiving module

Figure 1 Design scheme of RS layer receiving module

① Frame header detection and SLD localization. In the EPON system, the first 5 bytes of the preamble of an EPON frame are fixed, so the first 5 bytes can be used to determine the frame header. If the first 5 bytes of the received data are exactly the same as the first 5 bytes of the EPON frame, then the frame header is considered correct. That way, we can determine the location of the SLD byte. If the frame header is correct, the output signal Detect_dv will be 1, otherwise the output of Detect_dv will be 0. The output signal of the frame head detection and SLD positioning module is the Rxd [7:0] signal that enters the module.

② Counter. The main function of the counter module is to provide a selection signal output port for the 1 in 2 out module and a write enable signal for the FiFo management 1 module. It is controlled by the signal RX_dv, and when Rx_dv is 0, the counter clears to zero; When Rx_dv is 1, the counter will count normally. However, before counting to 8, its output signal is 0. When counting to 8, its output signal is only 1.

③ 1:2 selection. This is a signal selection output module, which is controlled by the counter output signal. When the output signal is 0, the signal enters the 1:2 module, outputs from port 1, and enters RAM1; When the output signal of the counter is 1, the signal entering the 1:2 module is output from port 2 and enters RAM2. That is to say, after the EPON frame undergoes frame head detection and SLD positioning, the preamble enters RAM1, and other bytes enter RAM2.

④ RAM1 and FiFo management 1. When the output signal of the counter is 0, after passing through the NOT gate, it becomes 1 and sends a write enable signal to FiFo Management 1. The FiFo Management 1 module provides a write address to write the signal output from Port 1 of the 1:2 module into RAM1 according to the address provided by the FiFo Management 1 module; Due to the 8 bytes of the preamble, the FiFo Management 1 module only provides 8 addresses; At the same time, it is also controlled by Detect_dv as the read enable signal. When the frame header detection is correct, Detect_dv is 1, which will trigger FiFo management 1 to provide a read address to RAM1. The address it provides is the byte that needs to be verified by CRC-8, so its read address is the address from the SLD domain to the LLID. This way, the byte to be verified will enter the CRC-8 module for cyclic redundancy verification.

⑤ RAM2 and FiFo management 2. When the output of the counter is 1, FiFo Management 2 provides an address for the data entering RAM2. The data from the frame head detection and SLD positioning modules enters RAM2 through a 1:2 selection module based on the address provided by FiFo Management 2 module. Then, based on the control signal obtained from the LLID matching module, the signal entering RAM2 is processed accordingly. When the received data carries a LLID that does not match the LLID assigned by the OLT to the local ONU, the FiFo management 2 module will cancel the address assigned to the incoming RAM2 data based on whether the received signal is cleared. As a result, the data cannot enter RAM2, and the data that does not match the LLID is discarded. When the received data LLID matches the allocated LLID, the LLID matching module will send a write enable signal to the FiFo Management 2 module, and the FiFo Management 2 module will provide the address of the signal to be read. This module is different from RAM1 and FiFo management 1 in that RAM2 reads data while also writing data.