Convolutional code is a commonly used error control encoding in deep space communication systems and wireless communication systems. It overcomes the disadvantage of block coding, which results in the loss of relevant information between groups due to encoding on a block by block basis. Convolutional codes (2, 1, 8) have been widely used in 2G and 3G communication systems. The forward channel of CDMA/IS-95 system [3] and the forward and backward links of CDMA20001x both use convolutional codes with a generating polynomial of (561753) and a rate of 1/2 (2,1,8). This paper proposes a new FPGA based (2, 1, 8) convolutional code decoder to address the drawbacks of high resource consumption and low maximum operating frequency in current convolutional code decoders. This decoder has a high operating frequency, low output delay, and occupies fewer resources.

Overall Design of 1 (2, 1, 8) Convolutional Code Decoder

The (2,1,8) convolutional code decoder implemented in this article is a hard decision decoder based on the Viterbi algorithm. The entire system of UAD149A1501 is divided into three unit modules: startup unit, intermediate processing unit, and decoding output unit. The overall system structure diagram is shown in Figure 1. For the (2, 1, 8) convolutional code decoder, the starting unit processes the first 8 input codewords, and the intermediate processing unit processes the subsequent input codewords. The decoding output unit realizes the output of code words translated by the decoder. In this design, the path metrics and survival paths of each state node are stored using registers within the FPGA chip, which is achieved through register swapping. This decoding output does not require backtracking, which can greatly improve the decoding speed of the decoder.

Design of Each Module for 2 (2, 1, 8) Convolutional Code Decoder

2.1 Starting Unit Module

The convolutional code decoder has a total of 256 state nodes. When processing the i-th (i is an integer greater than 0 and less than 9) of the first 8 input codewords, UAD149A1501 only needs to process the 2i state nodes, and there is only one previous state node that transitions to these 2i state nodes. The state transition diagram is shown in Figure 2. Therefore, there is no need to perform comparison and selection operations. The key to this unit is to determine which state nodes need to update their survival paths and path metrics when processing the i-th symbol. After analysis, it can be concluded that after the i-th symbol processing is completed. Only when the low (8-k) bits of the binary form of the state value corresponding to a node are all 0, can the decoder reach that state node. Based on this, this article proposes a clever method to determine whether a certain state node can be reached. Set an 8-bit wide register type variable sd0. Its initial value is set to 0x7f, which means its highest position is 0. After processing each symbol, sd0 is shifted to the right by one bit. When determining whether a node with a state value of i needs to be processed, sd0 and i are bitwise AND. If the result is 0, the state node needs to be processed. Otherwise, it directly enters the judgment processing of the next state node.

When calculating the path metric BM for each state node, this design adopts the following scheme. Pre calculate the encoding results of the 256 states of the (2, 1, 8) convolutional code when the input is 0, and store them in a register group of 256 bits with a width of 2 bits. When processing the received convolutional code codeword, the first step is to calculate the number of bits that are different from the four possible codewords 00, 01, 10, and 11 of the (2, 1, 8) convolutional code. And stored in the corresponding 4 2-bit wide path metric registers l0, l1, l2, and l3. Record the two path metrics of state node i and (i+128) as BM0 and BM1, respectively. The BM0 and BM1 of node i represent the number of bits that differ from the current input codeword when the encoder is in state (2xi) and (2xi+1) and the input is 0. The BM0 and BM1 of node (i+128) represent the number of bits that differ from the current input codeword when the encoder is in state (2xi) and (2xi+1) and the input is 1, respectively. And the sum of the two path metrics BM0 and BM1 for any state node is 2, based on which the values of BM0 and BM1 for each state node can be obtained.