Abstract: In response to the development requirements of 1553B communication module based on LXI instrument bus, a communication solution based on SOPC for 1553B bus is proposed. Supported by SOPC technology, embed Nios II soft core processor, Ethernet control component, 1553B control component, and RAM module on a single FPGA; By porting embedded real-time operating systems μ C/OS II and LwIP protocols, implementing TCP/IP protocol and 1553B bus protocol; Finally, the instrument driver program for the module was developed. The development difficulty of the design method in this article is low, the design module has a small volume, is easy to upgrade, and has strong engineering application and economic value.

Since the launch of LXI bus in September 2005, it has demonstrated numerous advantages in building testing systems. The CPCI-AC-6U-500 900-7002-99 testing system based on LXI bus has many advantages, such as ease of use, high flexibility, modularity and scalability, faster system throughput, distributed application, long lifespan, low cost, synchronization with IEEE1588 clock, small rack space, and synthetic instruments.

The full name of 1553B bus is “Time Division Command/Response Multiplex Data Bus”, which is used as a transmission bus by various weapon platforms such as fighter jets and warships in China. Therefore, the development of a 1553B communication module based on the LXI bus can not only meet the testing requirements of various types of weapons and equipment for the 1553B bus, but also promote the research and application of the LXI bus in China.

Overall Plan for Module 1

The basic design indicators of the module are: meeting the LXI standard for Class C instruments; CPCI-AC-6U-500 900-7002-99 supports DHCP, automatic configuration of IP addresses, and manual configuration of IP addresses; Supports ICMP protocol, TCP/IP protocol, and UDP protocol; Synchronize using network command mode; Capable of completing all functions of 1553B in BC mode.

According to the requirements of the indicators, a 32-bit processor based on SOPC and a Real Time Operation System (RTOS) overall solution are adopted. A controller and logic unit are integrated on a single FPGA chip, which not only reduces the difficulty of development, reduces module size, but also facilitates future upgrades. A 32-bit processor has sufficient resources to expand and utilize, RAM and ROM can be large enough, and the entire TCP/IP protocol family can be integrated into the system, even embedded in an operating system with TCP/IP protocol family.

Hardware Design and Development Based on SOPC

System on a Programmable Chip (SOPC) integrates the functional modules required for system design, such as processor, memory, I/O ports, LVDS, and CDR, into a PLD device to construct a programmable on-chip system. It is a flexible and efficient SOC solution. SOPC combines the advantages of SOC and programmable logic devices, with flexible design methods, customizable, expandable, and upgradable, and has the ability to program software and hardware in the system, becoming a new trend in SOC design.

2.1 Module Hardware Architecture

The module hardware mainly consists of 7 parts: Nios II soft core processor, Ethernet component, 1553B bus component, memory, on-chip RAM, universal I/O interface, and debugging configuration module. The architecture diagram is shown in Figure 1.

Figure 1 Hardware Architecture Diagram

Figure 1 Hardware Architecture Diagram

1) NiosII soft core processor: The CPU of a module, responsible for system work scheduling. Ported it internally μ C/OSII real-time operating system and LwIP protocol; It accepts requests sent by clients via Ethernet, analyzes them, and replies to the web interface or controls the 1553B functional interface; 2) Ethernet component (DM9000A): completes the operation of the Ethernet controller, sends the data on the network through the Ethernet controller to the Internet layer, and is processed by the LwIP protocol inside the NioslI soft core processor; Alternatively, the data sent from the Internet layer can be sent out through an Ethernet interface: 3) 1553B bus component (BU-61580): controlled by the NiosllI soft core processor, to complete the sending of various messages and commands in BC mode, as well as reading the status; 4) Flash memory: mainly used to store some fixed parameters of modules and static web interfaces; 5) On chip RAM: RAM is generated in the remaining logic of the FPGA using the MegaWizard manager included in Quartusll, so there is no need to add a RAM chip. On chip RAM is mainly used to store some data received and generated during program operation; 6) Universal I/O interface: used to control LEDs or buttons; 7) JTAG debugging module and EPCS configuration module: The J1TAG module is used to complete the debugging work of the program. Configuration is the process of programming the content of FPGA, which needs to be configured after each power on. The EPCS configuration module allows NioslI to access the EPCS serial configuration device.

The specific development mainly involves three parts of work: 1) the design of Nios II soft core processors and their peripherals. 2) The development of custom macro function module RAM is completed in QuartuslI software; 3) The writing of application software programs is completed in the NiosIIIDE software development environment.

2.2 Module Hardware Design

SOPC Builder is a tool developed by Altera for customizing systems for users. Users can use SOPC Builder to easily and quickly integrate complex system components such as IP cores, memory, interfaces, microprocessors, and custom components onto Athera high-density FPGA chips. According to the requirements of the module hardware system, the module hardware structure generated by SOPC Builder includes: 32-bit standard NiosII soft core processor: CPU; JTAG debugging interface: jtag debug module; External SDRAM memory interface: sdram; Avalon Tri State Bridge: tri_statebrid ge; EPCS serial flash controller: EPCS_controller; External FLASH memory interface: cfi_flash; Timer/counter: time0/timer; Ethernet interface: dm9000A; 1553B interface: bu61580; LED interface: LED; 64KRAM interface: RAM; Key interface: key; System recognition module: sysid.