ROLLS ROYCE MPC-300 TERMINAL CONTROLLER

ROLLS ROYCE MPC-300 TERMINAL CONTROLLER

In deep submicron level integrated circuit chips, the contribution of devices (transistors) to delay has become increasingly small, with the main delay being the connection delay. Due to the unique functionality of CP0, it has many connections with the storage management unit MMU and instruction counting unit PC, which are likely to be on the critical path of the entire chip; Moreover, due to the complex logic of CP0, the module generated by automatic layout and routing according to the standard unit method has a large area of its own, and some connections inside CP0 have to take many detours, which may cause significant delays. So it was decided to adopt a fully customized method to design the data path of CP0, in order to facilitate the control of the direction and layout of the wiring.
Division of Control and Data Paths
The normal operation of digital circuit systems involves data flow (including general data, instructions, and addresses) and control flow. And the data flow and control flow are relatively independent: the logic of data flow implementation is relatively simple, but there are many bits of data in parallel; The logic of control flow is relatively complex, with the vast majority being 1-bit or several bit control signals. Therefore, the control path generally does not adopt fully customized design; The fully customized design of data paths has the advantages of high performance, low power consumption, and low cost.
Assisting TLB in virtual to real address translation is one of the main functions of CP0. TLB is a privileged resource of the system, and only CP0 has access to it. Therefore, there are many connections between CP0 and TLB, and the latency of data exchange is also crucial. At the same time, the data exchange between PC modules and CP0 is also very important. Therefore, it is best for the CP0 unit to be close to both the TLB and PC modules on the layout. This design separates the logic and registers related to TLB in CP0 into CP0T and places them between the MMU and PC modules; The rest of CP0 is classified as CP0E and placed at the bottom of the PC, which is the lowest end of the entire chip. As shown in Figure 1.